A parallel hardware architecture for fast integral image computing

This paper proposes a method of fast integral image computing on hardware. We propose a high efficient hardware-based algorithm, and design a pipelined architecture suitable for our algorithm. Parallelism and time complexity of the algorithm are analyzed. And the hardware implementation of each operations of the algorithm is presented. Compared with two related works, we find that our architecture is of the highest efficiency, as it reaches the highest speed by consuming the comparatively lowest logic resources and power.