Area-efficient capacitor-less LDR with enhanced transient response for SoC in 65-nm CMOS

An output capacitor-less low-dropout regulator (LDR) with enhanced transient responses for system-on-a-chip (SoC) power management applications is presented in this paper. The boosted push-pull driving capability is realized by applying a transient-adaptively-biased folded-cascode error amplifier structure with a cross-coupled output stage that achieves higher dc gain and faster slew rate. The proposed LDR is compensated by combining active feedback (AFC) and adaptively-biased damping-factor-control (DFC) effectively. The idea of the LDR is implemented with a standard 65-nm CMOS process. The on-chip compensation capacitance is only 200fF. The output is 1.0V, which delivers a maximum current of 50mA at 200mV drop-out, and the output capacitor can be as large as 100pF. Extensive simulations verify that the proposed LDR can recover from 100ns-edged 10μA-50mA load transient and 1.2V-1.8V line transient in 200ns, with much reduced over-/under-shoot at the output.