Title :
A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS
Author :
Taek-Joon An ; Kyung-Sub Son ; Young-Jin Kim ; In-Seok Kong ; Jin-Ku Kang
Author_Institution :
Dept. of Electron. Eng., INHA Univ., Incheon, South Korea
Abstract :
The rapid growth of the data rate in serial links reveals the problem of power consumption, motivating utilization of low power building blocks. This paper presents a low-power clock and data recovery (CDR). By employing dynamic CML latch which draws a current during half of the clock cycle and voltage-to-current(V/I) converter which performs the XOR function itself, power reduction in phase detector(PD) is achieved. The CDR circuit is simulated using 5-Gb/s data with 0.18-μm CMOS technology, and the circuit consumes 8.7mW from a 1.8-V supply.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; low-power electronics; phase detectors; CMOS technology; XOR function; bit rate 5 Gbit/s; clock and data recovery circuit; dynamic CML latch; low power building blocks; phase detector; power 8.7 mW; serial links; size 0.18 mum; voltage 1.8 V; CMOS integrated circuits; Clocks; Latches; Logic gates; Power demand; Power dissipation; Voltage-controlled oscillators; Clock and Data Recovery(CDR); half-rate linear phase detector(PD);
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865638
