• DocumentCode
    1769320
  • Title

    A high-speed low-power calibrated flash ADC

  • Author

    Hsuan-Yu Chang ; Ching-Yuan Yang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan
  • fYear
    2014
  • fDate
    1-5 June 2014
  • Firstpage
    2369
  • Lastpage
    2372
  • Abstract
    A 2-GS/s 6-bit flash analog-to-digital converter (ADC) in 90nm CMOS is presented. Using the reference-voltage-interpolated calibration reduces bandwidth requirements on the comparator to enable high sampling rates with low power consumption. The ADC consumes 28 mW and occupies 0.35 mm2. The proposed calibrated technique improves ENOB from 3.0 to 5.1 with an input sinusoid at Nyquist frequency.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; low-power electronics; CMOS; Nyquist frequency; flash analog-to-digital converter; high-speed low-power calibrated flash ADC; low power consumption; power 28 mW; reference-voltage-interpolated calibration; size 90 nm; word length 6 bit; Accuracy; CMOS integrated circuits; Calibration; Capacitance; Power demand; Standards; Transistors; calibrated ADC; high sampling rate; low power;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
  • Conference_Location
    Melbourne VIC
  • Print_ISBN
    978-1-4799-3431-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2014.6865648
  • Filename
    6865648
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1769320