A 1.6 nS, 16µW, 30V Gm-C integrator for offset voltage monitoring in neural stimulators

The design of a CMOS integrator for offset voltage monitoring in implantable neural stimulation systems is presented. It reduces the risk of electrode dissolution and tissue destruction, which might arise from a residual electrode potential after unbalanced high voltage (HV) stimulation pulses. The integrator therefore requires HV robustness and low power consumption at the same time. Monitoring low frequency bio-potentials requests a very large time constant, while keeping the capacitance reasonably small for small chip area. The proposed integrator takes advantage of a transconductance-capacitance (G_m-C) approach. The described architecture is based on HV cross-coupled differential input pairs. Within a wide linear input range of ±3V, a time constant of 7.5 ms is achieved by an overall G_m of 1.6 nS and an integrated capacitance of 12 pF. It features a shift in voltage from a HV input common mode (CM) of 15V to a low voltage (LV) CM of 1.65V. The overall power dissipation of the G_m-C integrator is 16μW and the layout occupies 0.39mm². The system is designed in a 0.35μm CMOS technology with 30V supply and is verified by BSIM layout-extracted simulations.