Delay-line temperature sensors and VLSI thermal management demonstrated on a 60nm FPGA

This paper presents a thermal sensing and VLSI thermal management scheme using an array of on-chip all-digital delay-line based temperature sensors. A fully digital self-calibration method that removes the temperature sensors´ sensitivities to supply voltage and process variations is proposed. The proposed calibration method assigns a unique correction factor, N_C to each sensor, making all the sensors´ calibrated outputs to be the same at start-up. The correction factor is updated when supply voltage variations are detected. Only one calibration block is required to calibrate multiple delay-line based temperature sensors sequentially. For each additional sensor, only additional registers for storing N_C are required. The proposed self-calibrated temperature sensors are demonstrated on an Altera Cyclone IV FPGA based VLSI thermal management system. Runtime thermal profiles for four cores mapped on the Cyclone IV FPGA chip using a hybrid dynamic thermal management (DTM) method are obtained. The percentage of time that each core spent in a particular temperature range is plotted in a histogram. A comparison of different DTM techniques demonstrates that the proposed hybrid DTM reduces the amount of time that the MPSoC spent at higher temperatures and larger thermal gradients, by 10% and 21%, respectively. In addition, the proposed hybrid DTM offers a 10% improvement in the average processing rate (instructions per second) when compared with the conventional global DFS approach.