A high throughput CAVLC architecture design with two-path parallel coefficients procedure for digital cinema 4K resolution H.264/AVC encoding

In this paper, a high throughput context-based adaptive variable length code (CAVLC) encoder design with two-path parallel coefficients procedure is developed for H.264/AVC with block based pipelined and parallel processing schemes. By the two-pipe parallel coefficients processing, the proposed block processing based CAVLC encoder only requires 65 encoding cycles/macroblock (MB) on average. Compared with previous encoder designs, the throughput of the proposed architecture is improved over from 23% to 585%. The proposed encoding core modules have smaller area-time (AT) product performance than other designs. By VLSI implementations, the proposed CAVLC encoder can achieve Digital Cinema 4K, i.e. 4096×2160p@37Hz real-time video encoding.