Hardware transactional memory on multi-processor FPGA platform

Transactional memory (TM) is a promising approach in creating an abstraction layer for multi-threaded programming. However, the performance of TM is application-specific. Previous embedded system TM implementations exploit only conflict management to suit the application requirements. In this paper, we propose a hardware transactional memory (HTM) which exploits both version and conflict management. The proposed architecture is targeted for embedded applications and is area efficient compared to current methods that apply cache coherence protocols. The proposed system was tested with random requests at different contention levels. We implemented the HTM with four model processors on Cyclone IV Field Programmable Gate Array. Our results show that it offers up to 14% improvement in terms of clock cycle over the HTM scheme that only exploits conflict management.