Holographic algorithms for on-chip, non-boolean computing

It is widely believed that the established route of microelectronic scaling is approaching its end: further downscaling of semiconductor devices carries disproportionate penalties in power consumption and poses fundamental fabrication challenges. Instead of scaling of devices, Moore´s law is now increasingly about scaling computing systems: single-core devices toward larger, multi-core systems. While there are known programming methodologies for parallelizing program codes to a few threads, only very few, special-purpose applications lend themselves to parallelization on very large numbers of cores. This motivates our quest for studying computing paradigms and algorithms that are inherently parallel [1]. Holographic / optical computing is a perfect example of such algorithms: the results of a computation are given by an interference pattern formation of many light rays (see Fig. 1 for an illustration [1]). Optical systems are impractical to realize on-chip. For this reason, we explore routes to design holographic algorithms that can be naturally integrated with microelectronic technologies and require no optical hardware. Two approaches will be discussed in this paper.