Title :
On implementing packet inspection using CUDA enabled graphical processing units
Author :
Zoican, Sorin ; Vochin, Marius
Author_Institution :
Univ. Politeh. of Bucharest, Bucharest, Romania
Abstract :
This work has the goal to study how an efficient deep packet inspection (DPI) algorithm may be implemented using the graphical processing unit (GPU) CUDA (Computer Unified Device Architecture) enabled boards existing in personal computers, and to analyze implementation efficiency. The following tasks have been analyzed: the parallelization of the pattern matching algorithm and the optimization of C code written for Nvidia compiler to obtain the best performance. The conclusion shows that CUDA technology represents a very attractive solution to implement DPI algorithms without the typically memory and complexity constraints.
Keywords :
computer networks; graphics processing units; parallel algorithms; parallel architectures; pattern matching; C code optimization; CUDA enabled graphical processing units; Nvidia compiler; computer unified device architecture; deep packet inspection algorithm; pattern matching algorithm parallelization; Algorithm design and analysis; Computer architecture; Graphics processing units; Inspection; Instruction sets; Kernel; Registers; CUDA technology; deep packet inspection; deterministic finite automaton; pattern search; significant character;
Conference_Titel :
Communications (COMM), 2014 10th International Conference on
Conference_Location :
Bucharest
DOI :
10.1109/ICComm.2014.6866661
