Title :
Characterization of noise behavior of ultrathin inversion-channel and buried-channel SOI MOSFETs in the subthreshold bias range
Author :
Ito, T. ; Sato, S. ; Omura, Y.
Author_Institution :
Grad. Sch. Sci. & Eng., Kansai Univ., Suita, Japan
Abstract :
This paper considers aspects of low-frequency noise in the inversion-channel SOI nMOSFET and the buried-channel SOI pMOSFET. Analyses suggest that the inversion channel is strongly influenced by interface traps, which also weakly influence the buried-channel. It is demonstrated that such aspects are significant in the subthreshold bias range.
Keywords :
MOSFET; elemental semiconductors; interface states; semiconductor device noise; silicon; silicon-on-insulator; buried-channel SOI pMOSFET; interface trap; low-frequency noise behavior; subthreshold bias range; ultrathin inversion-channel SOI nMOSFET; Educational institutions; Electron traps; Logic gates; MOSFET; MOSFET circuits; Noise; Substrates; Low-frequency noise; SOI MOSFET; buried channel; inversion channel; subthreshold bias range;
Conference_Titel :
Future of Electron Devices, Kansai (IMFEDK), 2014 IEEE International Meeting for
Conference_Location :
Kyoto
Print_ISBN :
978-1-4799-3614-4
DOI :
10.1109/IMFEDK.2014.6867057
