DocumentCode :
177160
Title :
Modeling and Verifying the TTCAN Protocol Using Timed CSP
Author :
Qinwen Ran ; Xi Wu ; Xin Li ; Jianqi Shi ; Jian Guo ; Huibiao Zhu
fYear :
2014
fDate :
1-3 Sept. 2014
Firstpage :
90
Lastpage :
97
Abstract :
As one of the most practical protocols, Time-Triggered CAN protocol (TTCAN), which is time triggered to ensure the real-time capability required by embedded systems, has been widely used in the automotive electric system development. In this paper, we present a formal model of the TTCAN protocol using Timed Communicating Sequential Processes (Timed CSP). All the components in the protocol are abstracted as CSP processes, thus the basic transmission in TTCAN is converted into the communication between different CSP processes. Besides, an error handling model is also proposed to capture the exception in the protocol. Finally, we use model checker Process Analysis Toolkit (PAT) to verify whether we can achieve model caters for some properties, which are specified using Linear Temporal Logic (LTL) formulas. Based on the verification results, our TTCAN model turns out to match the specification.
Keywords :
communicating sequential processes; controller area networks; embedded systems; error handling; formal specification; formal verification; protocols; temporal logic; CSP process; LTL formula; PAT; TTCAN protocol; Timed CSP; automotive electric system development; embedded system; error handling model; formal model; linear temporal logic formula; model caters; model checker process analysis toolkit; real-time capability; time-triggered CAN protocol; timed CSP; timed communicating sequential process; Software engineering; Modeling; PAT; TTCAN protocol; Timed CSP; Verification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Theoretical Aspects of Software Engineering Conference (TASE), 2014
Conference_Location :
Changsha
Type :
conf
DOI :
10.1109/TASE.2014.8
Filename :
6976573
Link To Document :
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