Implementación de un algoritmo DSOGI-PLL en una FPGA para sincronización con la red de convertidores de potencia

Power converters are the subject of extensive research because of their ability to work under different operating conditions, providing bidirectional power flow, high dynamic range and fast response. These advantages allow them to be used as interface between the electric grid and many high power applications such as motors, energy storage, active filters and renewable energy sources. To be able to connect to the utility grid, every power converter must be provided with a synchronization method. The synchronization algorithms are mostly based on the well known SRF-PLL (Synchronous Reference Frame Phase Locked Loop) plus some pre-filter stage that can be achieved by different algorithms of variable complexity, usually implemented on DSPs (Digital Signal Processor) or Microcontrollers. In this paper a simple and highly effective FPGA (Field Programmable Gate Array) implementation of a PLL (Phase Locked Loop) algorithm based on a DSOGI-PLL (Dual Second Order Generalized Integrator Phase Locked Loop) is presented in detail, along with the auxiliary circuitry needed to acquire the grid voltage information. Using a fast-prototype high-level synthesis tool, design time is drastically reduced without the need of any HDL (Hardware Description Language) code. Both simulation with MATLAB Simulink and experimental results on a Xilinx SoC (System on Chip), show a robust behaviour even against frequency steps, severe distortion and unbalances in the power input.