Design of a 4th order LP ΣΔ modulator-what about non-idealities?

This modulator, a cascade hybrid proposal, takes advantage of both Continuous Time (CT) and Discrete Time (DT) approaches. In order to define a set of specifications Processing Basic-Blocks (PBBs) are firstly analyzed with the help of SIMSIDES. After that transistor-based simulations are carried out not only to verify fulfil specifications, but also to analyse the effect of non-idealities on the modulator performance. The expected response of the modulator is obtained by defining a set of experiments based on analytical models, which allow us to translate all design considerations into a set of values such that the design at transistor level be established according to the desired performance of the proposed architecture. This design strategy perhaps is not the most accurate but it allows us to get a general understanding of the system under design, and also a comprehension at the highest level of abstraction. The system under study is a cascade 4^th order hybrid Sigma-Delta (ΣΔ) modulator, from which the second stage is a 2^nd order Low-Pass (LP) DT ΣΔ modulator. The ideal performance of the DT modulator is used to show how non-idealities must be taken into account, and also how to translate design considerations into a set of physical values not only to design PBBs at transistor level, but also to minimize the non-idealities effects up to acceptable values.