Direct generation of upsampled FIR filter response a simple extension to filters with distributed arithmetic

A memory based upsampling/interpolating FIR filter modification/extension to distributed arithmetic (DA) based FIR filters is proposed that can be used for any filter coefficient set. Use of minimum or no multiplier is a desired design property when signal processing is performed using FPGAs since multipliers are scarce/expensive resources within FPGAs whereas registers and such are abundant. Upsampling a digital stream is usually performed by inserting zeros between original samples followed by a low pass filter to reject images. Compared to basic distributed arithmetic based filter designs where partial products/sums are stored in memory blocks, our design stores interpolation values. These samples are output sequentially using a simple counter, eliminating zero insertions and saving circuit elements. As an example FIR filter, we have designed a raised-cosine band-limiting filter with example roll-off factor and upsampling values. Successful implementation using VHDL+FPGA with ease has proven that the approach is a simple and effective compared to input upsampling.