DocumentCode :
1772784
Title :
Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs
Author :
Khan, Muhammad Asad ; Kerkhoff, Hans G.
Author_Institution :
Centre of Telematics & Inf. Technol., Univ. of Twente, Enschede, Netherlands
fYear :
2014
fDate :
23-25 April 2014
Firstpage :
15
Lastpage :
20
Abstract :
In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.
Keywords :
ageing; analogue-digital conversion; capacitors; digital-analogue conversion; virtual instrumentation; DAC capacitor-array degradation; LabVIEW environment; aging effects; aging-critical technology nodes; aging-related degradation effect simulation; buffer degradation; charge-redistribution SAR ADCs; comparator degradations; dynamic performance parameters; performance-analysis system; static performance parameters; successive approximation register; system-level behavioural models; transistor-level aging simulators; Aging; Arrays; Capacitors; Degradation; Mathematical model; Standards; Stress; DAC capacitor-array degradation; charge-redistribution SAR ADC; degradation modelling analysis; dependable design; sensitivity analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on
Conference_Location :
Warsaw
Print_ISBN :
978-1-4799-4560-3
Type :
conf
DOI :
10.1109/DDECS.2014.6868756
Filename :
6868756
Link To Document :
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