A double-path intra prediction architecture for the hardware H.265/HEVC encoder

This paper presents an innovatory approach to the design of the intra prediction architecture for the hardware H.265/HEVC (High Efficiency Video Coding) encoder. As the most of the computational complexity in the intra prediction algorithm is associated with the need to process number of 4×4 Prediction Units (PUs), an independent processing path is proposed for this specific PU size with a separate reconstruction loop. The final result from this path is then incorporated into the second path, independently checking all the remaining PUs. This approach does not entail a significant increase in utilization of hardware resources, while considerably accelerates the encoding. The proposed architecture can operate at 100 MHz for FPGA Aria II devices and at 200 MHz for the TSMC 0.13μm technology. The achieved throughput allows the processing of almost 17.5 and 35 1080p frames per second using FPGA and ASIC technology, respectively. The solution is compliant with the Main, Main 10, and Main Still Picture profiles of the H.265/HEVC standard.