Title :
A 64-MHz∼640-MHz 64-phase clock generator
Author :
Hong-Yi Huang ; Jen-Chieh Liu ; Shi-Jia Sun ; Cheng-Hao Fu ; Kuo-Hsing Cheng
Author_Institution :
Dept. of Electr. Eng., Nat. Taipei Univ., Taipei, Taiwan
Abstract :
This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of 500×620um2. The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.
Keywords :
CMOS integrated circuits; phase locked loops; voltage-controlled oscillators; CMOS process; all-digital phase locked loop; differential VCO; digital to voltage converter; frequency 64 MHz to 640 MHz; phase clock generator; size 0.18 mum; successive approximation register-controlled architecture; time 2.4 ps; time 20.5 ps; voltage controlled oscillator; Clocks; Delays; Frequency control; Phase locked loops; Radiation detectors; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on
Conference_Location :
Warsaw
Print_ISBN :
978-1-4799-4560-3
DOI :
10.1109/DDECS.2014.6868762
