Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators

Author

Balasubramaniam, Harish ; Hofmann, Klaus

Author_Institution

Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany

fYear

2014

fDate

23-25 April 2014

Firstpage

89

Lastpage

92

Abstract

This paper analyses the non-idealities of a second generation current conveyor (CCII) in advanced CMOS technologies. Primary sources of errors in the CCII are identified and their effects are analyzed with respect to its application as an integrator for delta sigma modulators. An improved CCII integrator architecture and a robust calibration algorithm are proposed to negate the CCII errors. The proposed integrator is used in the design of a 4^th order CCII based delta sigma modulator, simulation results of which reveal the advantages of proposed solution. The modulator designed in a 1V/90nm technology has a 78/70/46 dB DR and 77/69/45 dB SNDR for bandwidths of 2/4/10 MHz and clock frequency of 160 MHz respectively.

Keywords

CMOS integrated circuits; calibration; current conveyors; delta-sigma modulation; radiofrequency integrated circuits; 4^th order CCII; advanced CMOS technology; bandwidth 10 MHz; bandwidth 2 MHz; bandwidth 4 MHz; calibration algorithm; delta sigma modulator; frequency 160 MHz; integrator architecture; noise figure 45 dB; noise figure 46 dB; noise figure 69 dB; noise figure 70 dB; noise figure 77 dB; noise figure 78 dB; second generation current conveyor; Algorithm design and analysis; CMOS integrated circuits; Calibration; Capacitors; Charge transfer; Clocks; Modulation; CCII Analysis; CCII Integrator; Current Conveyors; Foreground Calibration; Sigma Delta Modulator;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on

Conference_Location

Warsaw

Print_ISBN

978-1-4799-4560-3

Type

conf

DOI

10.1109/DDECS.2014.6868769

Filename

6868769