Self-managing power management unit

Power consumption is a very important aspect in almost every electronic system design. To minimize the power consumption, many advanced power-reduction techniques have been developed based on a power management. In modern systems the power management unit (PMU) is typically a complex circuit and therefore should also be targeted by power-efficient design techniques. This paper is focused on the design of self-managing PMU that can manage its own power and thus reduce the overall system power consumption. We show that the special power state machine design in the PMU allows to power inactive transition logic elements down during the idle time. We illustrate this design strategy on a simple example where approximately 70% leakage power reduction in transition logic was achieved.