A study on fast pipelined pseudo-random number generator based on chaotic logistic map

In this paper we propose a novel design and FPGA implementation of high-speed pseudo-random number generator (PRNG) based on the pipelined processing and chaotic logistic map. An architecture of PRNG has been optimized to achieve maximum bit rate of output pseudo-random data stream. The PRNG has been examined for 16-, 32-, 48-, and 64-bit precision of arithmetic by NIST 800-22 tests performed for individual bit positions. Then, the final output data stream has been composed of selected bit positions and verified by NIST test again. The proposed architecture of PRNG has been implemented in a programmable system-on-chip device from a new Zynq family (Xilinx). Using this SoC chip with 28-nm programmable logic and dual core embedded processor we get the maximum generation rate equal to 11.2 Gbps.