FPGA design of the computation unit for the semi-global stereo matching algorithm

In recent years, it is possible to observe an increased interest in methods of stereo-vision as they allow simple 3D representations of the scene acquired with two optical cameras. However, not all methods described in literature are suitable for a real-time implementation in hardware. One method generally considered to produce good results and viable for such an implementation is semi-global stereo matching. Nevertheless, there are not many in-depth descriptions of hardware architectures of modules implementing this method in the literature. In this article we try to fill in this gap by presenting a detailed FPGA-oriented architecture of the basic computation unit supporting the semi-global matching algorithm. The unit is responsible for carrying out all calculation necessary to select the best disparity for each pixel. We also present a novel solution to the problem of storing paths´ costs for each pixel and discuss the trade-offs between the size of the unit in an FPGA chip and precision of the computed disparity map.