Title :
A unified CMOS inverter model for planar and FinFET nanoscale technologies
Author :
Chaourani, Panagiotis ; Nikolaidis, Spyridon
Author_Institution :
Phys. Dept., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece
Abstract :
In this paper, a new analytical model for describing the output waveform of the CMOS inverter for planar and FinFET nanoscale technologies, is introduced. A modified expression for the transistor current is adopted taken into account nano-scale effects like DIBL, CLM and NWE. The sub-threshold current of both transistors as well as their drain-to-bulk capacitances, which influence significantly the accuracy, are also considered. Results for 32nm planar and 20nm FinFET technologies validate the proposed model.
Keywords :
CMOS integrated circuits; MOSFET; capacitance; invertors; transistors; FinFET nanoscale technology; drain-to-bulk capacitance; planar nanoscale technology; size 20 nm; size 32 nm; transistor subthreshold current; unified CMOS inverter model; CMOS integrated circuits; FinFETs; Integrated circuit modeling; Inverters; Mathematical model; CMOS inverter; FinFETs; analytical model; nanoscale; timing analysis;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on
Conference_Location :
Warsaw
Print_ISBN :
978-1-4799-4560-3
DOI :
10.1109/DDECS.2014.6868799
