ADCs in deep submicron technologies for ASICs of pixel architecture

An important development in digital X-ray imaging systems is a pulse amplitude measurement in each pixel in real-time. A single readout pixel usually has the dimensions of 100 μm × 100 μm or lower, and as it has to accommodate the analog front-end amplifier and digital back-end readout logic, the area available for an ADC is extremely low. Thus, in the design of the ADC the most emphasis has to be put on decreasing its silicon area. Also, as a single readout chip consists of thousands of pixels, the allowed power budget per pixel is in the order of tens of microwatts, hence the power consumption of the converter has to be kept very low as well. This paper describes a design and measurement results of two 4-bit flash ADC prototypes, fabricated in 180 nm and 40 nm processes, which fit into a single pixel and can be used in future X-ray imaging systems. To make the comparison more meaningful, both designs share exactly the same architecture, have identical resolution and sample rate. The architecture of the design, layout comparison and obtained test results are presented.