FPGA architectures of the quantization and the dequantization for video encoders

In hardware video encoders, the quantization and dequantization modules can consume a significant amount of hardware resources. This paper presents optimization methods for FPGA architectures of the modules. The methods allow a better utilization of resources available in DSP units and the reduction of general-purpose logic elements. Different versions of architectures are developed for FPGA Altera Arria II devices. Implementation results show that the multiple reduction of general-purpose logic is achieved. Moreover, the utilization of registers embedded in DSP allows the doubled clock frequency.