DocumentCode
1772890
Title
An intra-cell defect grading tool
Author
Bosio, A. ; Dilillo, L. ; Girard, P. ; Todri-Sanial, A. ; Virazel, A. ; Bernabovi, S. ; Bernardi, P.
Author_Institution
LIRMM, Montpellier, France
fYear
2014
fDate
23-25 April 2014
Firstpage
298
Lastpage
301
Abstract
With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
Keywords
flip-flops; integrated circuit testing; scaling circuits; applied test set; continuous scaling; intra-cell defect grading tool; intra-cell defects; intra-cell diagnosis resolution; transistor size; Automatic test pattern generation; Circuit faults; Databases; Dictionaries; Integrated circuit modeling; Libraries; Logic gates; diagnosis; fault simulation; intra-cell defect; test;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on
Conference_Location
Warsaw
Print_ISBN
978-1-4799-4560-3
Type
conf
DOI
10.1109/DDECS.2014.6868814
Filename
6868814
Link To Document