Modeling and analysis of cracked through silicon via (TSV) interconnections

Author

Gerakis, Vasileios ; Avdikou, Christina ; Liolios, Alexandros ; Hatzopoulos, Alkis

Author_Institution

Dept. of Electr. & Comput. Eng., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece

fYear

2014

fDate

23-25 April 2014

Firstpage

310

Lastpage

313

Abstract

A lumped analytical electrical model for cracked (open fault) TSVs is proposed in this paper. Accurate and reliable fault models can support the test methods for the possible defects and they can be vital to improve the quality of TSV-based 3D-ICs. The model is verified by simulations using a commercial 3D resistance, capacitance and inductance extraction tool. The presented simulation results are in close agreement with the proposed analytical expressions.

Keywords

cracks; integrated circuit interconnections; integrated circuit modelling; three-dimensional integrated circuits; TSV-based 3D-IC quality; commercial 3D capacitance extraction tool; commercial 3D inductance extraction tool; commercial 3D resistance extraction tool; cracked TSV interconnection; cracked through silicon via interconnection; fault model; lumped analytical electrical model; Analytical models; Capacitance; Integrated circuit modeling; Mathematical model; Solid modeling; Three-dimensional displays; Through-silicon vias; 3D ICs; TSV; crack; fault modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on

Conference_Location

Warsaw

Print_ISBN

978-1-4799-4560-3

Type

conf

DOI

10.1109/DDECS.2014.6868817

Filename

6868817