A high-speed low-power multitask digital vision chip

A new pixel architecture for the use in a multitask digital vision chip is presented. The architecture is based on SIMD parallel processing, and it is configurable to perform different binary image processing operations in high speed and with low power consumption. The proposed circuit can output the result in each period of its operating frequency, which makes it very suitable for high speed real time applications. An array of 32*64 pixels has been simulated in 0.18 μm CMOS technology. The array works at 80 MHz clock frequency, and each pixel of it only consumes 3.4 μW. The results of image processing on the array show the high performance of the circuit.