Two-bit representation of the extrinsic LLR messages in the variable node processor of NB-LDPC decoder

This paper investigates a 2-bit binary representation of the reliability messages generated by the Variable Node (VN) processor of Non-Binary Low Density Parity Check (NB-LDPC) Decoder. The NB-LDPC family of error correcting codes, considered as a potential alternative to both binary LDPC and convolutional Turbo Codes, suffers from high computational complexity as well as large memory requirements. In order to reduce temporary storage requirements for extrinsic LLR messages, we propose a coding technique based on the 2-bit representation of the Log-Likelihood Ratio (LLR) messages generated locally in the VN processors. This simplified representation facilitates a size reduction of VN processor memory by 33% of the total memory size of extrinsic LLR messages. Monte Carlo simulations show that the 2-bit representation scheme has a negligible impact on the code performance.