FPGA-based simulation of power electronics using iterative methods

Real-time (RT) simulation is increasingly used in power electronics and power engineering as a tool to replace actual hardware for use in the development and verification of control and complex system designs. New computing architectures and algorithms, such as parallel and distributed computing, hold the promise to meet the speed requirement of such RT simulation. Due to its inherent parallelism at the hardware layer, field-programmable gate array (FPGA) provides an attractive alternative to conventional computing devices such as CPUs and GPUs for RT simulation. On the other hand, much of this advantage is lost when an FPGA is simply used as replacement for a CPU or GPU to execute existing simulation routines. This paper presents our preliminary work on the development of alternative circuit simulation algorithms that best exploit the parallelism and other unique features of FPGA for real-time simulation of power electronic converters and systems. Instead of solving the discretized circuit equations directly by inverting the coefficient matrix, we construct a signal flow diagram corresponding to solving the discretized model by the Jacobi iterative method. By exploiting the time-scale separation properties of typical power electronics circuits and properly selecting the discretizing time step, the response of the signal flow diagram can be made to converge to the original discretized circuit model response within a few iterations. Simulation of buck converter with average current control is used to illustrate and test the proposed method.