Lower error floor of LDPC codes based on trapping sets elimination

LDPC codes with excellent performance have great potential in applications of wireless mobile communications. However, the error floor phenomenon existing in LDPC codes limits its further application in disk storage and deep-space communications which require very low bit error rate (BER) system. The researchers find that trapping sets are the major reason why the LDPC codes have error floor. In this paper, we proposed an elimination algorithm to reduce small trapping sets. It was applying node rearrangement method to optimize the neighborhood of target nodes. In this way, cycles will be broken and the small size of trapping sets can be eliminated. The experimental results show that it can lower the error floor to improve the performance of LDPC codes. Besides, we also can keep the degree distribution, code rates and girth features of the original code with this method.