Study on the impact of CDFG on the design aspects of combinational logic circuits

CDFG plays the most important role in digital circuit design as it directly affects the area, speed and cost of the designed circuit. Hence in order to obtain an effective circuit, it is necessary to optimize CDFG. In this paper a detailed study on CDFGs for four different circuits is made for both pipelined and non-pipelined architecture. Performance is Measured in terms of number of circuit elements, delay and Balsa cost, it is found that the area complexity increases in the CDFGs of pipelined architectures. On the other hand, the CDFGs of non-pipelined architecture are computationally simpler. However latency decreases in the former when compared to the later.