High speed integer multiplier designs for reconfigurable systems

This work synthesises high performance integer multiplier designs suitable for high speed reconfigurable VLSI systems. Various designs of integer multipliers are taken and are compared on the basis of area and speed and the design most suited for the given FPGA platform is understood. The designs are implemented on Virtex FPGA and the comparisons in terms of area and speed are made. The multiplier design most suited for the given FPGA platform is thus understood. The designs are modeled using Verilog HDL, synthesized using Xilinx ISE 14.2 and finally implemented in Virtex 5 FPGAs.