Power reduction of one bit static ALU using D3L logic

Today´s electronic circuits utilizes large amount of data and so have very high power dissipation. Usually, the overall system performance depends on the interconnection scheme and the individual processing element. The individual processing elements are the main workhorses of the system and hence are critical to the total performance of the system. Arithmetic and Logic Unit(ALU) is a widely used processing element. If the power dissipation of ALU can be reduced then overall power dissipation can be reduced and performance can be improved. In this paper one bit static ALU is implemented using static CMOS logic gates. Static AND and OR gates of static ALU is replaced by Data Driven Dynamic Logic(D³L) AND and OR gates to compare the power dissipation. The power dissipation, delay and PDAP was reduced when D³L AND and OR gates were used.