High Slew Rate op-amp design for low power applications

This paper proposes a design of an Operational Amplifier which uses an Adaptive biasing circuitry along with an auxiliary circuit to improve the Slew Rate. One auxiliary circuit have been added to the differential amplifier in order to improve its Slew Rate. The Power Dissipation of the circuit is well controlled by the auxiliary circuit as auxiliary circuit comes into play only during large transients or slewing period and remains off during normal operation. Whenever an Operational Amplifier is driven as a voltage buffer, the output signal usually gets distorted even at very low frequencies. Thus by using the additional auxiliary circuit not only improves the Slew Rate at higher frequencies but also dissipates less power. The Operational Amplifier is designed and simulated using GPDK 90 nm CMOS technology in Cadence environment. It achieves a 40.09 dB DC gain, 31.31 V/μs Slew Rate for a load capacitor of 2 pF. A 105% improvement is achieved for slew rate. The core amplifier dissipates 92 μW.