DocumentCode
1776941
Title
A novel fast glitchless 7-3 counter with a new structure
Author
Ghasemzadeh, Mehdi ; Mohabbatian, Neda ; Akbari, Amin ; Hadidi, Khayrollah ; Khoei, Abdullah
Author_Institution
Microelectron. Res. Lab., Urmia Univ., Urmia, Iran
fYear
2014
fDate
19-21 June 2014
Firstpage
131
Lastpage
134
Abstract
This paper discusses about the design of a novel fast 7-3 counter for CMOS low power, high speed multiplier. In order to reduce delay and increase the speed, some changes have been made in the structure of the counters. Also the occupied area by the counter is decreased because of the less number of transistors. The delay of the proposed structure is 185ps which is simulated by HSPICE using TSMC 0.18μm CMOS technology.
Keywords
CMOS integrated circuits; SPICE; counting circuits; delays; multiplying circuits; CMOS; HSPICE; TSMC CMOS technology; fast glitchless 7-3 counter; high speed multiplier; low power multiplier; size 0.18 mum; Integrated circuits; counter; digital multiplier; low latency;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference
Conference_Location
Lublin
Print_ISBN
978-83-63578-03-9
Type
conf
DOI
10.1109/MIXDES.2014.6872171
Filename
6872171
Link To Document