A self-calibration technique for fast-switching frequency-hopped UWB synthesis

This paper presents a self-calibration technique for a fast-switching DLL-based frequency synthesizer targeting frequency-hopped ultra-wideband (UWB) communication. The proposed architecture employs the concept of track-and-hold (T/H) technique to sample the lock control voltages regarding each channel and store them across a corresponding capacitor during a start-up phase. During the normal operation when the hopping command arrives, the stored voltages are applied to the loop in an open-loop regime to perform fast channel switching of sub-9.5 ns which is required by WiMedia-UWB standard. Certain architectural and circuit methods are utilized in order to minimize the error in the sampled voltages caused by channel charge injection and clock feedthrough of the sampling switches. Since the proposed fast-switching scheme does not require a wide loop bandwidth, the existing tradeoff in phase-locked systems between the settling time and the control voltage ripples resulting in sideband spurs is eliminated. Moreover, the VCDL can be biased in the low-gain region of its transfer function to reduce its noise transfer to the synthesizer output. The proposed architecture is implemented in a 65-nm standard CMOS process and the simulation results indicate a worst-case band switching time of less than 5.5 ns.