How far can we push Si CMOS and what are the alternatives for future ULSI

Si CMOS technology has dominated the microelectronics industry, with continued scaling. However, future Si CMOS scaling is reaching practical and fundamental limits. Diminishing improvement in the on current and increase in off current are beginning to limit the scaling of bulk Si CMOS. Currently, strained-Si channel with high-k dielectric and metal gate is the dominant technology for high performance MOSFETs. Increasing the strain provides a viable solution to improve on current and high-k dielectrics provide lower gate leakage. Si FinFETs have provided another innovation to improve electrostatic control of the channel and thus reduce leakage. However, performance enhancement due to strain is beginning to saturate with scaling of nanoscale MOSFETs.