• DocumentCode
    1777243
  • Title

    Lateral versus vertical gate-all-around FETs for beyond 7nm technologies

  • Author

    Yakimets, D. ; Bao, T. Huynh ; Bardon, M.G. ; Dehan, M. ; Collaert, Nadine ; Mercha, Abdelkarim ; Tokei, Z. ; Thean, A. ; Verkest, D. ; De Meyer, K.

  • Author_Institution
    Imec, Leuven, Belgium
  • fYear
    2014
  • fDate
    22-25 June 2014
  • Firstpage
    133
  • Lastpage
    134
  • Abstract
    Nominal LG VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the LG is possible and it results in an extra 27% in IEFF in comparison to the nominal LG case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.
  • Keywords
    field effect transistors; BEOL-load; lateral gate-all-around FETs; nominal LG VFET-based RO; size 5 nm; size 7 nm; vertical gate-all-around FETs; Capacitance; Conductivity; Inverters; Layout; Logic gates; Resistance; Semiconductor process modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Device Research Conference (DRC), 2014 72nd Annual
  • Conference_Location
    Santa Barbara, CA
  • Print_ISBN
    978-1-4799-5405-6
  • Type

    conf

  • DOI
    10.1109/DRC.2014.6872333
  • Filename
    6872333
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1777243