Performance analysis of different SRAM cell topologies employing tunnel-FETs

Tunnel-FET is one of the most promising candidates to replace CMOS in low-power (LP) applications [1], featuring a sub-threshold slope (SS) below the 60mV/dec limit of MOSFET. However, the intrinsic asymmetry of TFETs, makes them good transistors only for a current flowing from drain to source and prevents their use as access transistors (AT) in the 6T SRAM cell. In this paper, we use TCAD mixed device-circuit simulations [2] of symmetric 6T SRAM cells, implemented with the n-type SiGe/Si TFET and p-type strained-Si TFET designed in [3] (Fig. 1) for V_DD as low as 0.2V. The gate metal work-functions were set to match the off-current for LP applications (10pA/μm). For comparison purposes, both N- and P-MOS were also designed with the same double-gate SOI structure. The I_D-V_GS curves of the TFETs (Fig.2) show that the sub-60mV/decade region is confined to ultra low voltage regime (below 0.25 V) and that ambipolarity is very limited in these devices. I_D(V_DS) in Fig.3 show the lower output conductance of the TFETs w.r.t. to MOS.