Title : 
Ultra-thin-body self-aligned InGaAs MOSFETs on insulator (III-V-O-I) by a tight-pitch process
         
        
            Author : 
Jianqiang Lin ; Czornomaz, L. ; Daix, N. ; Antoniadis, Dimitri A. ; del Alamo, Jesus A.
         
        
            Author_Institution : 
Microsyst. Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA
         
        
        
        
        
        
            Abstract : 
We report a self-aligned InGaAs Quantum-Well MOSFET (QW-MOSFET) on III-V-O-I substrate fabricated through a tight-pitch process. The ultra-thin body (UTB) III-V-O-I layer structure was fabricated on Si through a direct bonding technique. The III-V MOSFETs, with a self-aligned gate and metal contacts, were fabricated by a gate-last method. For the first time, we demonstrate adjacent devices with contact metal spacing of 150 nm. The fabrication features CMOS compatibility with a wet-etch free, lift-off free and Au-free process in the front end. Transport and short-channel effects (SCE) are studied as a function of back bias. Excellent SCE control is obtained with DIBL and subthreshold swing benchmarked against state-of-the-art III-V-O-I data. The reported technology provides a new path to integrate III-V front-end devices for future high density circuit applications.
         
        
            Keywords : 
CMOS analogue integrated circuits; III-V semiconductors; MOSFET; gallium arsenide; indium compounds; quantum well devices; CMOS compatibility; III-V MOSFET; III-V front-end devices; III-V-O-I substrate; InGaAs; QW-MOSFET; SCE control; UTB III-V-O-I layer structure; back bias function; contact metal spacing; direct bonding technique; gate-last method; gold-free process; high-density circuit application; lift-off-free process; metal contact; quantum-well MOSFET; self-aligned gate; short-channel effects; silicon; subthreshold swing; tight-pitch process; transport effects; ultrathin-body self-aligned indium gallium arsenide MOSFET; wet-etch-free process; Fabrication; Indium gallium arsenide; Indium phosphide; Logic gates; MOSFET; Silicon; Substrates;
         
        
        
        
            Conference_Titel : 
Device Research Conference (DRC), 2014 72nd Annual
         
        
            Conference_Location : 
Santa Barbara, CA
         
        
            Print_ISBN : 
978-1-4799-5405-6
         
        
        
            DOI : 
10.1109/DRC.2014.6872375