Influence of InP source/drain layers upon the DC characteristics of InAs/InGaAs MOSFETs

Because of the low effective mass, MOSFETs using In-rich (x>53%) In_xGa_1-xAs channels [1-5] exhibit high on-state current I_on at low drain bias (V_DS=0.5 V). However, the small bandgap of high-indium In_xGa_1-xAs channels can lead to high off-state leakage I_off due to band-to-band tunneling (BTBT) and impact ionization (I.I.). Earlier we had reported [1] that adding an unintentionally-doped (U.I.D.) InGaAs vertical spacer within the raised source/drain (S/D) of an InAs/InGaAs channel MOSFET substantially reduced I_off. Here we compare the characteristics of FETs using a wide-bandgap U.I.D. InP vertical spacer to earlier results [1] using an InGaAs spacer, and to control devices using only a very thin spacer. We find that FETs using InP spacers have I_off comparable to FETs using narrower-bandgap InGaAs spacers of similar thickness, suggesting that with the spacer, the observed I_off at high V_DS arises from BTBT or I.I. within the channel, and not within the high-field gate-drain spacer layer. Further, the wide-gap U.I.D. InP source spacer does not increase the threshold voltage V_th, suggesting that the gated potential barrier remains in the channel and not in the source spacer region. We also compare the on-state characteristics of FETs using InAs/InGaAs channels and an N+ InP S/D. Unlike the findings of [6], we do not observe improved I_on with the use of a wider-bandgap N+ source.