ESD co-design methodologies for RF and mmW circuits

Summary form only given. One of the bottlenecks of introducing CMOS RF and millimeter wave (mmW) circuits to the market is their susceptibility to electrostatic discharge (ESD). It is due to both gate oxide breakdown and junction degradation related problems, caused by the thinner gate oxide thickness and increased doping levels of state-of-the-art CMOS processes. On the other hand, the increasing operation frequency range makes the ESD protection design a great challenge. The parasitic effects of the on-chip ESD devices on the RF path often degrade the power gain, noise figure and linearity of the RF and mmW front-ends, especially the low noise amplifier (LNA) input stage. Therefore, there is a strong motivation to simultaneously optimize RF performance and provide ESD protection for RF and mmW circuits. The talk will introduce to RFIC designers the state-of-the-art techniques, such as inductive cancellation or impedance isolation techniques, to simultaneously fulfill the requirements of both the RF performance and ESD protection. Two design cases will be presented. First, the design of a decreasing-sized-model electrostatic discharge (ESD) protection structure applied to protect against ESD stresses at the RF input pad of an ultra-low power CMOS front-end operating in the 2.4-GHz industrial-scientific- medical band. This structure can sustain a human body-model ESD level higher than 16 kV and a machine-model ESD level higher than 1 kV without degrading the RF performance of the front-end. Second, an area efficient Electrostatic Discharge (ESD) protection structure to protect the RF input PAD of a 77 GHz low noise amplifier (LNA) in a 65nm CMOS process. The proposed RF-ESD protection co-design using an inductive cancellation method can handle Transmission Line Pulse (TLP) ESD currents up to more than 2.7A without RF performance degradation, which corresponds to an equivalent 4.05 kV voltage level of the human body model (HBM).