A 10 bit 12.8 MS/s SAR analog-to-digital converter in a 250 nm SiGe BiCMOS technology

This paper presents a 10 bit 12.8 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a 250 nm SiGe BiCMOS technology. An energy-efficient switching algorithm with top-plate sampling is applied which reduces the total input capacitance by 50%. High-impedance inputs with emitter followers and internal reference voltage generation make it suitable for applications that require precise on-chip voltage monitoring. For a low-frequency input signal, measured SNDR and SFDR of the presented SAR ADC are 48.7 dB and 57.8 dB. The effective resolution bandwidth (ERBW) is 19 MHz. The ADC draws 17.4 rnA from a 2.6 V supply including reference voltage generation, clock drivers and emitter follower buffers for input and reference voltages. The die area is 2.1 × 0.7 mm² with the ADC core occupying 1 × 0.5 mm². A formula for relating static nonlinearity (INL) measurements with dynamic SNDRIENOB measurements is derived. From output codes recorded with constant input voltages, the distortion power caused by nonlinearity and the noise of the reference voltage source and the comparator are determined. After adapting them to sinusoidal inputs, the expected impact on SNDR and ENOB is derived.