• DocumentCode
    1778156
  • Title

    From an analytic NBTI device model to reliability assessment of complex digital circuits

  • Author

    Aryan, Naser Pour ; Listl, A. ; Heiss, L. ; Yilmaz, Cemal ; Georgakos, Georg ; Schmitt-Landsiedel, Doris

  • Author_Institution
    Tech. Univ. Muenchen, Munich, Germany
  • fYear
    2014
  • fDate
    7-9 July 2014
  • Firstpage
    19
  • Lastpage
    24
  • Abstract
    In safety critical applications precise characterization of circuits to predict the lifetime reliability is a key challenge. This paper proposes a reliability assessment tool to model and simulate the NBTI degradation including its recovery effect during the design phase of digital circuits. The model is based on single device models and the corresponding measurement data. The circuits under test can be custom designed on transistor level and/or designed on gate level. The toolset is applied to a test circuit to evaluate its reliability within the lifetime. Considering not only the permanent component of NBTI but also the recoverable part, the tool provides a useful means to prevent an early circuit failure at minimum costs. Our studies support the applicability of the proposed method to efficiently estimate application specific reliability requirements over lifetime.
  • Keywords
    circuit reliability; circuit testing; digital circuits; negative bias temperature instability; network synthesis; NBTI device model; circuit under test; complex digital circuit; gate level design; lifetime reliability assessment; safety critical application; transistor level design; Aging; Degradation; Integrated circuit modeling; Logic gates; Reliability; Stress; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International
  • Conference_Location
    Platja d´Aro, Girona
  • Type

    conf

  • DOI
    10.1109/IOLTS.2014.6873666
  • Filename
    6873666