• DocumentCode
    1778198
  • Title

    A hybrid reliability assessment method and its support of sequential logic modelling

  • Author

    Pagliarini, Samuel N. ; de B Naviner, Lirida A. ; Naviner, Jean-Francois ; Pradhan, Dhiraj

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK
  • fYear
    2014
  • fDate
    7-9 July 2014
  • Firstpage
    182
  • Lastpage
    183
  • Abstract
    This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.
  • Keywords
    integrated circuit modelling; integrated circuit reliability; sequential circuits; digital circuits; hybrid reliability assessment method; logic masking; modified hybrid method; multiple-fault occurrence; sequential logic modelling; Circuit faults; Integrated circuit modeling; Integrated circuit reliability; Logic gates; Sequential circuits; Transient analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International
  • Conference_Location
    Platja d´Aro, Girona
  • Type

    conf

  • DOI
    10.1109/IOLTS.2014.6873690
  • Filename
    6873690
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1778198