Automated synthesis of cell libraries for asynchronous circuits

Asynchronous techniques are regaining relevance in the VLSI research community as they allow increasing robustness against process variability considerably, by relaxing timing assumptions. In addition, asynchronous circuits enable achieving low-power and high-speed designs. However, due to the absence of commercial dedicated standard cell libraries to take the most of asynchronous design, such circuits implementations are relegated to full-custom approaches only. This limits applicability of asynchronous solutions and avoids further development of dedicated design automation tools. This paper describes an improvement to this situation by proposing a fully-automated design-flow called ASCEnD-A, able to implement standard cells specifically required for asynchronous circuits design. The flow is capable of generating cells at the layout level, providing physical, power and timing models required by cell-based flows available in the state-of-the-art technologies.