Synthesis of a phase locked loop system for a control system of the three-phase active voltage rectifier

Phase locked loop (PLL) system implementation in information subsystem of active voltage rectifier (AVR) is determined by requirement of power factor correction and suppression of the higher harmonics in current reference signal in nonideal mains voltage conditions. The method of phase locked loop system synthesis based on state space formalism is proposed. Control algorithm is based on state feedback control principals which means using a feedback signal composed from the components of the object´s state as the controlled input. State regulator for PLL control system is synthesized. For immeasurable object´s states estimation reduced-order observer is used. Digital PLL system synthesis is provided. Transition from differential equations of state to the difference equations of state is carried out to describe processes in the digital control system. The model of three-phase active voltage rectifier with synthesized phase locked loop is made. Modelling results shows the capability of AVR control system with synthesized PLL to carry out compensation of reactive power and to correct current shape in the mains.