SiGe channel deposition by batch epitaxy

SiGe channels have been introduced for Global-foundries 32nm HKMG Gate-First CMOS technology to control the PFET V_T [1], In order to reduce the cost of ownership for this this additional process step by a factor of 3 an epitaxial batch system described by Kunii et al. [2] has been introduced into high volume production. An initial evaluation of the batch tool shows that morphology and device performance are mainly matched to those of the single wafer tool at the studied thickness range, no pattern loading effect has been observed and the variability of the thickness which is critical for V_T variation is clearly reduced [1], However, since the tool concept is very different to that of the widely used single wafer tools, there are some tool specific issues that need to be managed.