III–V/Ge CMOS device technologies for future logic LSIs

CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future [1, 2]. There can be several CMOS structures using III-V/Ge channels, as schematically shown in Fig. 1. Viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies of III-V/Ge MOS devices. Here, one of the most important issues for applying to the future technology nodes is suppression of short channel effects, which can be realized by ultrathin body (UTB) channels. Particularly, we would prefer planar UTB/UTBOX-based structures, which can realize further improvement of SCEs by combination with multi-gate structures such as FinFET and Tri-gate/nanowire MOSFETs, as shown in Fig. 2. This scheme allows us to provide static and/or dynamic Vth control through UTBOX by Si substrate doping and back bias under simple structures and fabrication processes. As for Ge-based CMOS, easy integration of GOI/SGOI is possible under the present SOI/sSOI platform. Here, the difficult challenges for realizing high performance logic devices include the III-V/Ge ultrathin body channel formation, the low resistivity S/D formation, the mobility enhancement in such ultrathin body channels and superior MOS gate stacks. Our approach for the channel formation is the wafer bonding and the Ge condensation. Also, metal S/D technologies are regarded as promising for reducing parasitic S/D resistance. In order to maintain high channel mobility, we employ optimized channel design of quantum wells (QW) with MOS interface buffers for III-V channels, and surface orientation and strain engineering for Ge channels. The GeO_x-based gate stacks are important for obtaining high mobility Ge MOSFETs with ultrathin EOT.